diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore
index 09653aa29c..4e9d499738 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/.gitignore
@@ -11,8 +11,11 @@ EventRecorderStub.scvd
# STM32CubeIDE autogenerated files.
.settings/
+*.launch
# Build Artifacts
Debug/
Listings/
Objects/
+BrowseInfo/
+BuildLogs/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h
index ab45ee9da8..bbfb3caf63 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Config/FreeRTOSConfig.h
@@ -139,4 +139,6 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
* used. TEX=0, S=0, C=1, B=1. */
#define configTEX_S_C_B_SRAM ( 0x03UL )
+/* Do not allow critical sections from unprivileged tasks. */
+#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0
#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c
new file mode 100644
index 0000000000..3c02e6921f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/GCC/reg_tests_asm.c
@@ -0,0 +1,988 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * "Reg test" tasks - These fill the registers with known values, then check
+ * that each register maintains its expected value for the lifetime of the
+ * task. Each task uses a different set of values. The reg test tasks execute
+ * with a very low priority, so get preempted very frequently. A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ */
+/*-----------------------------------------------------------*/
+
+/* Functions that implement reg tests. */
+void vRegTest1Asm( void ) __attribute__( ( naked ) );
+void vRegTest2Asm( void ) __attribute__( ( naked ) );
+void vRegTest3Asm( void ) __attribute__( ( naked ) );
+void vRegTest4Asm( void ) __attribute__( ( naked ) );
+/*-----------------------------------------------------------*/
+
+void vRegTest1Asm( void ) /* __attribute__( ( naked ) ) */
+{
+ __asm volatile
+ (
+ ".extern ulRegTest1LoopCounter \n"
+ ".syntax unified \n"
+ " \n"
+ " /* Fill the core registers with known values. */ \n"
+ " movs r0, #100 \n"
+ " movs r1, #101 \n"
+ " movs r2, #102 \n"
+ " movs r3, #103 \n"
+ " movs r4, #104 \n"
+ " movs r5, #105 \n"
+ " movs r6, #106 \n"
+ " movs r7, #107 \n"
+ " mov r8, #108 \n"
+ " mov r9, #109 \n"
+ " mov r10, #110 \n"
+ " mov r11, #111 \n"
+ " mov r12, #112 \n"
+ " \n"
+ " /* Fill the FPU registers with known values. */ \n"
+ " vmov.f32 s1, #1.5 \n"
+ " vmov.f32 s2, #2.5 \n"
+ " vmov.f32 s3, #3.5 \n"
+ " vmov.f32 s4, #4.5 \n"
+ " vmov.f32 s5, #5.5 \n"
+ " vmov.f32 s6, #6.5 \n"
+ " vmov.f32 s7, #7.5 \n"
+ " vmov.f32 s8, #8.5 \n"
+ " vmov.f32 s9, #9.5 \n"
+ " vmov.f32 s10, #10.5 \n"
+ " vmov.f32 s11, #11.5 \n"
+ " vmov.f32 s12, #12.5 \n"
+ " vmov.f32 s13, #13.5 \n"
+ " vmov.f32 s14, #14.5 \n"
+ " vmov.f32 s15, #1.0 \n"
+ " vmov.f32 s16, #2.0 \n"
+ " vmov.f32 s17, #3.0 \n"
+ " vmov.f32 s18, #4.0 \n"
+ " vmov.f32 s19, #5.0 \n"
+ " vmov.f32 s20, #6.0 \n"
+ " vmov.f32 s21, #7.0 \n"
+ " vmov.f32 s22, #8.0 \n"
+ " vmov.f32 s23, #9.0 \n"
+ " vmov.f32 s24, #10.0 \n"
+ " vmov.f32 s25, #11.0 \n"
+ " vmov.f32 s26, #12.0 \n"
+ " vmov.f32 s27, #13.0 \n"
+ " vmov.f32 s28, #14.0 \n"
+ " vmov.f32 s29, #1.5 \n"
+ " vmov.f32 s30, #2.5 \n"
+ " vmov.f32 s31, #3.5 \n"
+ " \n"
+ "reg1_loop: \n"
+ " \n"
+ " /* Verify that core registers contain correct values. */ \n"
+ " cmp r0, #100 \n"
+ " bne reg1_error_loop \n"
+ " cmp r1, #101 \n"
+ " bne reg1_error_loop \n"
+ " cmp r2, #102 \n"
+ " bne reg1_error_loop \n"
+ " cmp r3, #103 \n"
+ " bne reg1_error_loop \n"
+ " cmp r4, #104 \n"
+ " bne reg1_error_loop \n"
+ " cmp r5, #105 \n"
+ " bne reg1_error_loop \n"
+ " cmp r6, #106 \n"
+ " bne reg1_error_loop \n"
+ " cmp r7, #107 \n"
+ " bne reg1_error_loop \n"
+ " cmp r8, #108 \n"
+ " bne reg1_error_loop \n"
+ " cmp r9, #109 \n"
+ " bne reg1_error_loop \n"
+ " cmp r10, #110 \n"
+ " bne reg1_error_loop \n"
+ " cmp r11, #111 \n"
+ " bne reg1_error_loop \n"
+ " cmp r12, #112 \n"
+ " bne reg1_error_loop \n"
+ " \n"
+ " /* Verify that FPU registers contain correct values. */ \n"
+ " vmov.f32 s0, #1.5 \n" /* s0 = 1.5. */
+ " vcmp.f32 s1, s0 \n" /* Compare s0 and s1. */
+ " vmrs APSR_nzcv, FPSCR \n" /* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne to work. */
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #2.5 \n"
+ " vcmp.f32 s2, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #3.5 \n"
+ " vcmp.f32 s3, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #4.5 \n"
+ " vcmp.f32 s4, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #5.5 \n"
+ " vcmp.f32 s5, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #6.5 \n"
+ " vcmp.f32 s6, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #7.5 \n"
+ " vcmp.f32 s7, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #8.5 \n"
+ " vcmp.f32 s8, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #9.5 \n"
+ " vcmp.f32 s9, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #10.5 \n"
+ " vcmp.f32 s10, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #11.5 \n"
+ " vcmp.f32 s11, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #12.5 \n"
+ " vcmp.f32 s12, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #13.5 \n"
+ " vcmp.f32 s13, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #14.5 \n"
+ " vcmp.f32 s14, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #1.0 \n"
+ " vcmp.f32 s15, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #2.0 \n"
+ " vcmp.f32 s16, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #3.0 \n"
+ " vcmp.f32 s17, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #4.0 \n"
+ " vcmp.f32 s18, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #5.0 \n"
+ " vcmp.f32 s19, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #6.0 \n"
+ " vcmp.f32 s20, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #7.0 \n"
+ " vcmp.f32 s21, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #8.0 \n"
+ " vcmp.f32 s22, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #9.0 \n"
+ " vcmp.f32 s23, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #10.0 \n"
+ " vcmp.f32 s24, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #11.0 \n"
+ " vcmp.f32 s25, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #12.0 \n"
+ " vcmp.f32 s26, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #13.0 \n"
+ " vcmp.f32 s27, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #14.0 \n"
+ " vcmp.f32 s28, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #1.5 \n"
+ " vcmp.f32 s29, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #2.5 \n"
+ " vcmp.f32 s30, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " vmov.f32 s0, #3.5 \n"
+ " vcmp.f32 s31, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg1_error_loop \n"
+ " \n"
+ " /* Everything passed, inc the loop counter. */ \n"
+ " push { r0, r1 } \n"
+ " ldr r0, =ulRegTest1LoopCounter \n"
+ " ldr r1, [r0] \n"
+ " adds r1, r1, #1 \n"
+ " str r1, [r0] \n"
+ " \n"
+ " /* Yield to increase test coverage. */ \n"
+ " movs r0, #0x01 \n"
+ " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR */
+ " lsls r0, #28 \n" /* Shift to PendSV bit */
+ " str r0, [r1] \n"
+ " dsb \n"
+ " pop { r0, r1 } \n"
+ " \n"
+ " /* Start again. */ \n"
+ " b reg1_loop \n"
+ " \n"
+ "reg1_error_loop: \n"
+ " /* If this line is hit then there was an error in \n"
+ " * a core register value. The loop ensures the \n"
+ " * loop counter stops incrementing. */ \n"
+ " b reg1_error_loop \n"
+ " nop \n"
+ ".ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRegTest2Asm( void ) /* __attribute__( ( naked ) ) */
+{
+ __asm volatile
+ (
+ ".extern ulRegTest2LoopCounter \n"
+ ".syntax unified \n"
+ " \n"
+ " /* Fill the core registers with known values. */ \n"
+ " movs r0, #0 \n"
+ " movs r1, #1 \n"
+ " movs r2, #2 \n"
+ " movs r3, #3 \n"
+ " movs r4, #4 \n"
+ " movs r5, #5 \n"
+ " movs r6, #6 \n"
+ " movs r7, #7 \n"
+ " mov r8, #8 \n"
+ " mov r9, #9 \n"
+ " movs r10, #10 \n"
+ " movs r11, #11 \n"
+ " movs r12, #12 \n"
+ " \n"
+ " /* Fill the FPU registers with known values. */ \n"
+ " vmov.f32 s1, #1.0 \n"
+ " vmov.f32 s2, #2.0 \n"
+ " vmov.f32 s3, #3.0 \n"
+ " vmov.f32 s4, #4.0 \n"
+ " vmov.f32 s5, #5.0 \n"
+ " vmov.f32 s6, #6.0 \n"
+ " vmov.f32 s7, #7.0 \n"
+ " vmov.f32 s8, #8.0 \n"
+ " vmov.f32 s9, #9.0 \n"
+ " vmov.f32 s10, #10.0 \n"
+ " vmov.f32 s11, #11.0 \n"
+ " vmov.f32 s12, #12.0 \n"
+ " vmov.f32 s13, #13.0 \n"
+ " vmov.f32 s14, #14.0 \n"
+ " vmov.f32 s15, #1.5 \n"
+ " vmov.f32 s16, #2.5 \n"
+ " vmov.f32 s17, #3.5 \n"
+ " vmov.f32 s18, #4.5 \n"
+ " vmov.f32 s19, #5.5 \n"
+ " vmov.f32 s20, #6.5 \n"
+ " vmov.f32 s21, #7.5 \n"
+ " vmov.f32 s22, #8.5 \n"
+ " vmov.f32 s23, #9.5 \n"
+ " vmov.f32 s24, #10.5 \n"
+ " vmov.f32 s25, #11.5 \n"
+ " vmov.f32 s26, #12.5 \n"
+ " vmov.f32 s27, #13.5 \n"
+ " vmov.f32 s28, #14.5 \n"
+ " vmov.f32 s29, #1.0 \n"
+ " vmov.f32 s30, #2.0 \n"
+ " vmov.f32 s31, #3.0 \n"
+ " \n"
+ "reg2_loop: \n"
+ " \n"
+ " /* Verify that core registers contain correct values. */ \n"
+ " cmp r0, #0 \n"
+ " bne reg2_error_loop \n"
+ " cmp r1, #1 \n"
+ " bne reg2_error_loop \n"
+ " cmp r2, #2 \n"
+ " bne reg2_error_loop \n"
+ " cmp r3, #3 \n"
+ " bne reg2_error_loop \n"
+ " cmp r4, #4 \n"
+ " bne reg2_error_loop \n"
+ " cmp r5, #5 \n"
+ " bne reg2_error_loop \n"
+ " cmp r6, #6 \n"
+ " bne reg2_error_loop \n"
+ " cmp r7, #7 \n"
+ " bne reg2_error_loop \n"
+ " cmp r8, #8 \n"
+ " bne reg2_error_loop \n"
+ " cmp r9, #9 \n"
+ " bne reg2_error_loop \n"
+ " cmp r10, #10 \n"
+ " bne reg2_error_loop \n"
+ " cmp r11, #11 \n"
+ " bne reg2_error_loop \n"
+ " cmp r12, #12 \n"
+ " bne reg2_error_loop \n"
+ " \n"
+ " /* Verify that FPU registers contain correct values. */ \n"
+ " vmov.f32 s0, #1.0 \n"
+ " vcmp.f32 s1, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #2.0 \n"
+ " vcmp.f32 s2, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #3.0 \n"
+ " vcmp.f32 s3, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #4.0 \n"
+ " vcmp.f32 s4, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #5.0 \n"
+ " vcmp.f32 s5, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #6.0 \n"
+ " vcmp.f32 s6, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #7.0 \n"
+ " vcmp.f32 s7, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #8.0 \n"
+ " vcmp.f32 s8, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #9.0 \n"
+ " vcmp.f32 s9, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #10.0 \n"
+ " vcmp.f32 s10, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #11.0 \n"
+ " vcmp.f32 s11, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #12.0 \n"
+ " vcmp.f32 s12, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #13.0 \n"
+ " vcmp.f32 s13, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #14.0 \n"
+ " vcmp.f32 s14, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #1.5 \n"
+ " vcmp.f32 s15, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #2.5 \n"
+ " vcmp.f32 s16, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #3.5 \n"
+ " vcmp.f32 s17, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #4.5 \n"
+ " vcmp.f32 s18, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #5.5 \n"
+ " vcmp.f32 s19, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #6.5 \n"
+ " vcmp.f32 s20, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #7.5 \n"
+ " vcmp.f32 s21, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #8.5 \n"
+ " vcmp.f32 s22, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #9.5 \n"
+ " vcmp.f32 s23, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #10.5 \n"
+ " vcmp.f32 s24, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #11.5 \n"
+ " vcmp.f32 s25, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #12.5 \n"
+ " vcmp.f32 s26, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #13.5 \n"
+ " vcmp.f32 s27, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #14.5 \n"
+ " vcmp.f32 s28, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #1.0 \n"
+ " vcmp.f32 s29, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #2.0 \n"
+ " vcmp.f32 s30, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " vmov.f32 s0, #3.0 \n"
+ " vcmp.f32 s31, s0 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg2_error_loop \n"
+ " \n"
+ " /* Everything passed, inc the loop counter. */ \n"
+ " push { r0, r1 } \n"
+ " ldr r0, =ulRegTest2LoopCounter \n"
+ " ldr r1, [r0] \n"
+ " adds r1, r1, #1 \n"
+ " str r1, [r0] \n"
+ " pop { r0, r1 } \n"
+ " \n"
+ " /* Start again. */ \n"
+ " b reg2_loop \n"
+ " \n"
+ "reg2_error_loop: \n"
+ " /* If this line is hit then there was an error in \n"
+ " * a core register value. The loop ensures the \n"
+ " * loop counter stops incrementing. */ \n"
+ " b reg2_error_loop \n"
+ " nop \n"
+ ".ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRegTest3Asm( void ) /* __attribute__( ( naked ) ) */
+{
+ __asm volatile
+ (
+ ".extern ulRegTest3LoopCounter \n"
+ ".syntax unified \n"
+ " \n"
+ " /* Fill the core registers with known values. */ \n"
+ " movs r0, #100 \n"
+ " movs r1, #101 \n"
+ " movs r2, #102 \n"
+ " movs r3, #103 \n"
+ " movs r4, #104 \n"
+ " movs r5, #105 \n"
+ " movs r6, #106 \n"
+ " movs r7, #107 \n"
+ " mov r8, #108 \n"
+ " mov r9, #109 \n"
+ " mov r10, #110 \n"
+ " mov r11, #111 \n"
+ " mov r12, #112 \n"
+ " \n"
+ " /* Fill the FPU registers with known values. */ \n"
+ " vmov.f32 s0, #1.5 \n"
+ " vmov.f32 s2, #2.0 \n"
+ " vmov.f32 s3, #3.5 \n"
+ " vmov.f32 s4, #4.0 \n"
+ " vmov.f32 s5, #5.5 \n"
+ " vmov.f32 s6, #6.0 \n"
+ " vmov.f32 s7, #7.5 \n"
+ " vmov.f32 s8, #8.0 \n"
+ " vmov.f32 s9, #9.5 \n"
+ " vmov.f32 s10, #10.0 \n"
+ " vmov.f32 s11, #11.5 \n"
+ " vmov.f32 s12, #12.0 \n"
+ " vmov.f32 s13, #13.5 \n"
+ " vmov.f32 s14, #14.0 \n"
+ " vmov.f32 s15, #1.5 \n"
+ " vmov.f32 s16, #2.0 \n"
+ " vmov.f32 s17, #3.5 \n"
+ " vmov.f32 s18, #4.0 \n"
+ " vmov.f32 s19, #5.5 \n"
+ " vmov.f32 s20, #6.0 \n"
+ " vmov.f32 s21, #7.5 \n"
+ " vmov.f32 s22, #8.0 \n"
+ " vmov.f32 s23, #9.5 \n"
+ " vmov.f32 s24, #10.0 \n"
+ " vmov.f32 s25, #11.5 \n"
+ " vmov.f32 s26, #12.0 \n"
+ " vmov.f32 s27, #13.5 \n"
+ " vmov.f32 s28, #14.0 \n"
+ " vmov.f32 s29, #1.5 \n"
+ " vmov.f32 s30, #2.0 \n"
+ " vmov.f32 s31, #3.5 \n"
+ " \n"
+ "reg3_loop: \n"
+ " \n"
+ " /* Verify that core registers contain correct values. */ \n"
+ " cmp r0, #100 \n"
+ " bne reg3_error_loop \n"
+ " cmp r1, #101 \n"
+ " bne reg3_error_loop \n"
+ " cmp r2, #102 \n"
+ " bne reg3_error_loop \n"
+ " cmp r3, #103 \n"
+ " bne reg3_error_loop \n"
+ " cmp r4, #104 \n"
+ " bne reg3_error_loop \n"
+ " cmp r5, #105 \n"
+ " bne reg3_error_loop \n"
+ " cmp r6, #106 \n"
+ " bne reg3_error_loop \n"
+ " cmp r7, #107 \n"
+ " bne reg3_error_loop \n"
+ " cmp r8, #108 \n"
+ " bne reg3_error_loop \n"
+ " cmp r9, #109 \n"
+ " bne reg3_error_loop \n"
+ " cmp r10, #110 \n"
+ " bne reg3_error_loop \n"
+ " cmp r11, #111 \n"
+ " bne reg3_error_loop \n"
+ " cmp r12, #112 \n"
+ " bne reg3_error_loop \n"
+ " \n"
+ " /* Verify that FPU registers contain correct values. */ \n"
+ " vmov.f32 s1, #1.5 \n"
+ " vcmp.f32 s0, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #2.0 \n"
+ " vcmp.f32 s2, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #3.5 \n"
+ " vcmp.f32 s3, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #4.0 \n"
+ " vcmp.f32 s4, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #5.5 \n"
+ " vcmp.f32 s5, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #6.0 \n"
+ " vcmp.f32 s6, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #7.5 \n"
+ " vcmp.f32 s7, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #8.0 \n"
+ " vcmp.f32 s8, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #9.5 \n"
+ " vcmp.f32 s9, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #10.0 \n"
+ " vcmp.f32 s10, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #11.5 \n"
+ " vcmp.f32 s11, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #12.0 \n"
+ " vcmp.f32 s12, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #13.5 \n"
+ " vcmp.f32 s13, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #14.0 \n"
+ " vcmp.f32 s14, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #1.5 \n"
+ " vcmp.f32 s15, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #2.0 \n"
+ " vcmp.f32 s16, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #3.5 \n"
+ " vcmp.f32 s17, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #4.0 \n"
+ " vcmp.f32 s18, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #5.5 \n"
+ " vcmp.f32 s19, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #6.0 \n"
+ " vcmp.f32 s20, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #7.5 \n"
+ " vcmp.f32 s21, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #8.0 \n"
+ " vcmp.f32 s22, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #9.5 \n"
+ " vcmp.f32 s23, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #10.0 \n"
+ " vcmp.f32 s24, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #11.5 \n"
+ " vcmp.f32 s25, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #12.0 \n"
+ " vcmp.f32 s26, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #13.5 \n"
+ " vcmp.f32 s27, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #14.0 \n"
+ " vcmp.f32 s28, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #1.5 \n"
+ " vcmp.f32 s29, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #2.0 \n"
+ " vcmp.f32 s30, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " vmov.f32 s1, #3.5 \n"
+ " vcmp.f32 s31, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg3_error_loop \n"
+ " \n"
+ " /* Everything passed, inc the loop counter. */ \n"
+ " push { r0, r1 } \n"
+ " ldr r0, =ulRegTest3LoopCounter \n"
+ " ldr r1, [r0] \n"
+ " adds r1, r1, #1 \n"
+ " str r1, [r0] \n"
+ " \n"
+ " /* Yield to increase test coverage. */ \n"
+ " movs r0, #0x01 \n"
+ " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR */
+ " lsls r0, #28 \n" /* Shift to PendSV bit */
+ " str r0, [r1] \n"
+ " dsb \n"
+ " pop { r0, r1 } \n"
+ " \n"
+ " /* Start again. */ \n"
+ " b reg3_loop \n"
+ " \n"
+ "reg3_error_loop: \n"
+ " /* If this line is hit then there was an error in \n"
+ " * a core register value. The loop ensures the \n"
+ " * loop counter stops incrementing. */ \n"
+ " b reg3_error_loop \n"
+ " nop \n"
+ ".ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRegTest4Asm( void ) /* __attribute__( ( naked ) ) */
+{
+ __asm volatile
+ (
+ ".extern ulRegTest4LoopCounter \n"
+ ".syntax unified \n"
+ " \n"
+ " /* Fill the core registers with known values. */ \n"
+ " movs r0, #0 \n"
+ " movs r1, #1 \n"
+ " movs r2, #2 \n"
+ " movs r3, #3 \n"
+ " movs r4, #4 \n"
+ " movs r5, #5 \n"
+ " movs r6, #6 \n"
+ " movs r7, #7 \n"
+ " mov r8, #8 \n"
+ " mov r9, #9 \n"
+ " movs r10, #10 \n"
+ " movs r11, #11 \n"
+ " movs r12, #12 \n"
+ " \n"
+ " /* Fill the FPU registers with known values. */ \n"
+ " vmov.f32 s0, #1.5 \n"
+ " vmov.f32 s2, #2.0 \n"
+ " vmov.f32 s3, #3.0 \n"
+ " vmov.f32 s4, #4.5 \n"
+ " vmov.f32 s5, #5.0 \n"
+ " vmov.f32 s6, #6.0 \n"
+ " vmov.f32 s7, #7.5 \n"
+ " vmov.f32 s8, #8.0 \n"
+ " vmov.f32 s9, #9.0 \n"
+ " vmov.f32 s10, #10.5 \n"
+ " vmov.f32 s11, #11.0 \n"
+ " vmov.f32 s12, #12.0 \n"
+ " vmov.f32 s13, #13.5 \n"
+ " vmov.f32 s14, #14.0 \n"
+ " vmov.f32 s15, #1.0 \n"
+ " vmov.f32 s16, #2.5 \n"
+ " vmov.f32 s17, #3.0 \n"
+ " vmov.f32 s18, #4.0 \n"
+ " vmov.f32 s19, #5.5 \n"
+ " vmov.f32 s20, #6.0 \n"
+ " vmov.f32 s21, #7.0 \n"
+ " vmov.f32 s22, #8.5 \n"
+ " vmov.f32 s23, #9.0 \n"
+ " vmov.f32 s24, #10.0 \n"
+ " vmov.f32 s25, #11.5 \n"
+ " vmov.f32 s26, #12.0 \n"
+ " vmov.f32 s27, #13.0 \n"
+ " vmov.f32 s28, #14.5 \n"
+ " vmov.f32 s29, #1.0 \n"
+ " vmov.f32 s30, #2.0 \n"
+ " vmov.f32 s31, #3.5 \n"
+ " \n"
+ "reg4_loop: \n"
+ " \n"
+ " /* Verify that core registers contain correct values. */ \n"
+ " cmp r0, #0 \n"
+ " bne reg4_error_loop \n"
+ " cmp r1, #1 \n"
+ " bne reg4_error_loop \n"
+ " cmp r2, #2 \n"
+ " bne reg4_error_loop \n"
+ " cmp r3, #3 \n"
+ " bne reg4_error_loop \n"
+ " cmp r4, #4 \n"
+ " bne reg4_error_loop \n"
+ " cmp r5, #5 \n"
+ " bne reg4_error_loop \n"
+ " cmp r6, #6 \n"
+ " bne reg4_error_loop \n"
+ " cmp r7, #7 \n"
+ " bne reg4_error_loop \n"
+ " cmp r8, #8 \n"
+ " bne reg4_error_loop \n"
+ " cmp r9, #9 \n"
+ " bne reg4_error_loop \n"
+ " cmp r10, #10 \n"
+ " bne reg4_error_loop \n"
+ " cmp r11, #11 \n"
+ " bne reg4_error_loop \n"
+ " cmp r12, #12 \n"
+ " bne reg4_error_loop \n"
+ " \n"
+ " /* Verify that FPU registers contain correct values. */ \n"
+ " vmov.f32 s1, #1.5 \n"
+ " vcmp.f32 s0, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #2.0 \n"
+ " vcmp.f32 s2, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #3.0 \n"
+ " vcmp.f32 s3, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #4.5 \n"
+ " vcmp.f32 s4, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #5.0 \n"
+ " vcmp.f32 s5, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #6.0 \n"
+ " vcmp.f32 s6, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #7.5 \n"
+ " vcmp.f32 s7, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #8.0 \n"
+ " vcmp.f32 s8, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #9.0 \n"
+ " vcmp.f32 s9, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #10.5 \n"
+ " vcmp.f32 s10, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #11.0 \n"
+ " vcmp.f32 s11, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #12.0 \n"
+ " vcmp.f32 s12, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #13.5 \n"
+ " vcmp.f32 s13, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #14.0 \n"
+ " vcmp.f32 s14, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #1.0 \n"
+ " vcmp.f32 s15, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #2.5 \n"
+ " vcmp.f32 s16, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #3.0 \n"
+ " vcmp.f32 s17, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #4.0 \n"
+ " vcmp.f32 s18, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #5.5 \n"
+ " vcmp.f32 s19, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #6.0 \n"
+ " vcmp.f32 s20, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #7.0 \n"
+ " vcmp.f32 s21, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #8.5 \n"
+ " vcmp.f32 s22, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #9.0 \n"
+ " vcmp.f32 s23, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #10.0 \n"
+ " vcmp.f32 s24, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #11.5 \n"
+ " vcmp.f32 s25, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #12.0 \n"
+ " vcmp.f32 s26, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #13.0 \n"
+ " vcmp.f32 s27, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #14.5 \n"
+ " vcmp.f32 s28, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #1.0 \n"
+ " vcmp.f32 s29, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #2.0 \n"
+ " vcmp.f32 s30, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " vmov.f32 s1, #3.5 \n"
+ " vcmp.f32 s31, s1 \n"
+ " vmrs APSR_nzcv, FPSCR \n"
+ " bne reg4_error_loop \n"
+ " \n"
+ " /* Everything passed, inc the loop counter. */ \n"
+ " push { r0, r1 } \n"
+ " ldr r0, =ulRegTest4LoopCounter \n"
+ " ldr r1, [r0] \n"
+ " adds r1, r1, #1 \n"
+ " str r1, [r0] \n"
+ " pop { r0, r1 } \n"
+ " \n"
+ " /* Start again. */ \n"
+ " b reg4_loop \n"
+ " \n"
+ "reg4_error_loop: \n"
+ " /* If this line is hit then there was an error in \n"
+ " * a core register value. The loop ensures the \n"
+ " * loop counter stops incrementing. */ \n"
+ " b reg4_error_loop \n"
+ " nop \n"
+ ".ltorg \n"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/IAR/reg_tests_asm.s b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/IAR/reg_tests_asm.s
new file mode 100644
index 0000000000..8e3345994b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/IAR/reg_tests_asm.s
@@ -0,0 +1,956 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * "Reg test" - These fill the registers with known values, then check
+ * that each register maintains its expected value for the lifetime of the
+ * task. Each task uses a different set of values. The reg test tasks execute
+ * with a very low priority, so get preempted very frequently. A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ */
+
+/*-----------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+
+ EXTERN ulRegTest1LoopCounter
+ EXTERN ulRegTest2LoopCounter
+ EXTERN ulRegTest3LoopCounter
+ EXTERN ulRegTest4LoopCounter
+
+ PUBLIC vRegTest1Asm
+ PUBLIC vRegTest2Asm
+ PUBLIC vRegTest3Asm
+ PUBLIC vRegTest4Asm
+/*-----------------------------------------------------------*/
+
+vRegTest1Asm:
+ /* Fill the core registers with known values. */
+ movs r0, #100
+ movs r1, #101
+ movs r2, #102
+ movs r3, #103
+ movs r4, #104
+ movs r5, #105
+ movs r6, #106
+ movs r7, #107
+ movs r8, #108
+ movs r9, #109
+ movs r10, #110
+ movs r11, #111
+ movs r12, #112
+
+ vmov.f32 s1, #1.5
+ vmov.f32 s2, #2.5
+ vmov.f32 s3, #3.5
+ vmov.f32 s4, #4.5
+ vmov.f32 s5, #5.5
+ vmov.f32 s6, #6.5
+ vmov.f32 s7, #7.5
+ vmov.f32 s8, #8.5
+ vmov.f32 s9, #9.5
+ vmov.f32 s10, #10.5
+ vmov.f32 s11, #11.5
+ vmov.f32 s12, #12.5
+ vmov.f32 s13, #13.5
+ vmov.f32 s14, #14.5
+ vmov.f32 s15, #1.0
+ vmov.f32 s16, #2.0
+ vmov.f32 s17, #3.0
+ vmov.f32 s18, #4.0
+ vmov.f32 s19, #5.0
+ vmov.f32 s20, #6.0
+ vmov.f32 s21, #7.0
+ vmov.f32 s22, #8.0
+ vmov.f32 s23, #9.0
+ vmov.f32 s24, #10.0
+ vmov.f32 s25, #11.0
+ vmov.f32 s26, #12.0
+ vmov.f32 s27, #13.0
+ vmov.f32 s28, #14.0
+ vmov.f32 s29, #1.5
+ vmov.f32 s30, #2.5
+ vmov.f32 s31, #3.5
+
+ reg1_loop:
+ cmp r0, #100
+ bne reg1_error_loop
+ cmp r1, #101
+ bne reg1_error_loop
+ cmp r2, #102
+ bne reg1_error_loop
+ cmp r3, #103
+ bne reg1_error_loop
+ cmp r4, #104
+ bne reg1_error_loop
+ cmp r5, #105
+ bne reg1_error_loop
+ cmp r6, #106
+ bne reg1_error_loop
+ cmp r7, #107
+ bne reg1_error_loop
+ cmp r8, #108
+ bne reg1_error_loop
+ cmp r9, #109
+ bne reg1_error_loop
+ cmp r10, #110
+ bne reg1_error_loop
+ cmp r11, #111
+ bne reg1_error_loop
+ cmp r12, #112
+ bne reg1_error_loop
+
+ /* Verify that FPU registers contain correct values. */
+ vmov.f32 s0, #1.5
+ vcmp.f32 s1, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #2.5
+ vcmp.f32 s2, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #3.5
+ vcmp.f32 s3, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #4.5
+ vcmp.f32 s4, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #5.5
+ vcmp.f32 s5, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #6.5
+ vcmp.f32 s6, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #7.5
+ vcmp.f32 s7, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #8.5
+ vcmp.f32 s8, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #9.5
+ vcmp.f32 s9, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #10.5
+ vcmp.f32 s10, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #11.5
+ vcmp.f32 s11, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #12.5
+ vcmp.f32 s12, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #13.5
+ vcmp.f32 s13, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #14.5
+ vcmp.f32 s14, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #1.0
+ vcmp.f32 s15, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #2.0
+ vcmp.f32 s16, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #3.0
+ vcmp.f32 s17, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #4.0
+ vcmp.f32 s18, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #5.0
+ vcmp.f32 s19, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #6.0
+ vcmp.f32 s20, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #7.0
+ vcmp.f32 s21, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #8.0
+ vcmp.f32 s22, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #9.0
+ vcmp.f32 s23, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #10.0
+ vcmp.f32 s24, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #11.0
+ vcmp.f32 s25, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #12.0
+ vcmp.f32 s26, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #13.0
+ vcmp.f32 s27, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #14.0
+ vcmp.f32 s28, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #1.5
+ vcmp.f32 s29, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #2.5
+ vcmp.f32 s30, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+ vmov.f32 s0, #3.5
+ vcmp.f32 s31, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg1_error_loop
+
+ /* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest1LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+
+ /* Yield to increase test coverage. */
+ movs r0, #0x01
+ ldr r1, =0xe000ed04 /* NVIC_ICSR. */
+ lsls r0, r0, #28 /* Shift to PendSV bit. */
+ str r0, [r1]
+ dsb
+ pop { r0, r1 }
+
+ /* Start again. */
+ b reg1_loop
+
+ reg1_error_loop:
+ b reg1_error_loop
+ nop
+ ltorg /* Create a literal pool to ensure that the constants accessed in the above
+ * code are not out of range. */
+
+/*-----------------------------------------------------------*/
+
+vRegTest2Asm:
+ /* Fill the core registers with known values. */
+ movs r0, #0
+ movs r1, #1
+ movs r2, #2
+ movs r3, #3
+ movs r4, #4
+ movs r5, #5
+ movs r6, #6
+ movs r7, #7
+ mov r8, #8
+ mov r9, #9
+ movs r10, #10
+ movs r11, #11
+ movs r12, #12
+
+ /* Fill the FPU registers with known values. */
+ vmov.f32 s1, #1.0
+ vmov.f32 s2, #2.0
+ vmov.f32 s3, #3.0
+ vmov.f32 s4, #4.0
+ vmov.f32 s5, #5.0
+ vmov.f32 s6, #6.0
+ vmov.f32 s7, #7.0
+ vmov.f32 s8, #8.0
+ vmov.f32 s9, #9.0
+ vmov.f32 s10, #10.0
+ vmov.f32 s11, #11.0
+ vmov.f32 s12, #12.0
+ vmov.f32 s13, #13.0
+ vmov.f32 s14, #14.0
+ vmov.f32 s15, #1.5
+ vmov.f32 s16, #2.5
+ vmov.f32 s17, #3.5
+ vmov.f32 s18, #4.5
+ vmov.f32 s19, #5.5
+ vmov.f32 s20, #6.5
+ vmov.f32 s21, #7.5
+ vmov.f32 s22, #8.5
+ vmov.f32 s23, #9.5
+ vmov.f32 s24, #10.5
+ vmov.f32 s25, #11.5
+ vmov.f32 s26, #12.5
+ vmov.f32 s27, #13.5
+ vmov.f32 s28, #14.5
+ vmov.f32 s29, #1.0
+ vmov.f32 s30, #2.0
+ vmov.f32 s31, #3.0
+
+ reg2_loop:
+ /* Verify that core registers contain correct values. */
+ cmp r0, #0
+ bne reg2_error_loop
+ cmp r1, #1
+ bne reg2_error_loop
+ cmp r2, #2
+ bne reg2_error_loop
+ cmp r3, #3
+ bne reg2_error_loop
+ cmp r4, #4
+ bne reg2_error_loop
+ cmp r5, #5
+ bne reg2_error_loop
+ cmp r6, #6
+ bne reg2_error_loop
+ cmp r7, #7
+ bne reg2_error_loop
+ cmp r8, #8
+ bne reg2_error_loop
+ cmp r9, #9
+ bne reg2_error_loop
+ cmp r10, #10
+ bne reg2_error_loop
+ cmp r11, #11
+ bne reg2_error_loop
+ cmp r12, #12
+ bne reg2_error_loop
+
+ /* Verify that FPU registers contain correct values. */
+ vmov.f32 s0, #1.0
+ vcmp.f32 s1, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #2.0
+ vcmp.f32 s2, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #3.0
+ vcmp.f32 s3, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #4.0
+ vcmp.f32 s4, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #5.0
+ vcmp.f32 s5, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #6.0
+ vcmp.f32 s6, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #7.0
+ vcmp.f32 s7, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #8.0
+ vcmp.f32 s8, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #9.0
+ vcmp.f32 s9, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #10.0
+ vcmp.f32 s10, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #11.0
+ vcmp.f32 s11, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #12.0
+ vcmp.f32 s12, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #13.0
+ vcmp.f32 s13, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #14.0
+ vcmp.f32 s14, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #1.5
+ vcmp.f32 s15, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #2.5
+ vcmp.f32 s16, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #3.5
+ vcmp.f32 s17, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #4.5
+ vcmp.f32 s18, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #5.5
+ vcmp.f32 s19, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #6.5
+ vcmp.f32 s20, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #7.5
+ vcmp.f32 s21, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #8.5
+ vcmp.f32 s22, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #9.5
+ vcmp.f32 s23, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #10.5
+ vcmp.f32 s24, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #11.5
+ vcmp.f32 s25, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #12.5
+ vcmp.f32 s26, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #13.5
+ vcmp.f32 s27, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #14.5
+ vcmp.f32 s28, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #1.0
+ vcmp.f32 s29, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #2.0
+ vcmp.f32 s30, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+ vmov.f32 s0, #3.0
+ vcmp.f32 s31, s0
+ vmrs APSR_nzcv, FPSCR
+ bne reg2_error_loop
+
+ /* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest2LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0, r1 }
+
+ /* Start again. */
+ b reg2_loop
+
+ reg2_error_loop:
+ b reg2_error_loop
+ nop
+ ltorg /* Create a literal pool to ensure that the constants accessed in the above
+ * code are not out of range. */
+
+/*-----------------------------------------------------------*/
+
+vRegTest3Asm:
+ /* Fill the core registers with known values. */
+ movs r0, #100
+ movs r1, #101
+ movs r2, #102
+ movs r3, #103
+ movs r4, #104
+ movs r5, #105
+ movs r6, #106
+ movs r7, #107
+ mov r8, #108
+ mov r9, #109
+ mov r10, #110
+ mov r11, #111
+ mov r12, #112
+
+ /* Fill the FPU registers with known values. */
+ vmov.f32 s0, #1.5
+ vmov.f32 s2, #2.0
+ vmov.f32 s3, #3.5
+ vmov.f32 s4, #4.0
+ vmov.f32 s5, #5.5
+ vmov.f32 s6, #6.0
+ vmov.f32 s7, #7.5
+ vmov.f32 s8, #8.0
+ vmov.f32 s9, #9.5
+ vmov.f32 s10, #10.0
+ vmov.f32 s11, #11.5
+ vmov.f32 s12, #12.0
+ vmov.f32 s13, #13.5
+ vmov.f32 s14, #14.0
+ vmov.f32 s15, #1.5
+ vmov.f32 s16, #2.0
+ vmov.f32 s17, #3.5
+ vmov.f32 s18, #4.0
+ vmov.f32 s19, #5.5
+ vmov.f32 s20, #6.0
+ vmov.f32 s21, #7.5
+ vmov.f32 s22, #8.0
+ vmov.f32 s23, #9.5
+ vmov.f32 s24, #10.0
+ vmov.f32 s25, #11.5
+ vmov.f32 s26, #12.0
+ vmov.f32 s27, #13.5
+ vmov.f32 s28, #14.0
+ vmov.f32 s29, #1.5
+ vmov.f32 s30, #2.0
+ vmov.f32 s31, #3.5
+
+ reg3_loop:
+ /* Verify that core registers contain correct values. */
+ cmp r0, #100
+ bne reg3_error_loop
+ cmp r1, #101
+ bne reg3_error_loop
+ cmp r2, #102
+ bne reg3_error_loop
+ cmp r3, #103
+ bne reg3_error_loop
+ cmp r4, #104
+ bne reg3_error_loop
+ cmp r5, #105
+ bne reg3_error_loop
+ cmp r6, #106
+ bne reg3_error_loop
+ cmp r7, #107
+ bne reg3_error_loop
+ cmp r8, #108
+ bne reg3_error_loop
+ cmp r9, #109
+ bne reg3_error_loop
+ cmp r10, #110
+ bne reg3_error_loop
+ cmp r11, #111
+ bne reg3_error_loop
+ cmp r12, #112
+ bne reg3_error_loop
+
+ /* Verify that FPU registers contain correct values. */
+ vmov.f32 s1, #1.5
+ vcmp.f32 s0, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s2, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s3, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #4.0
+ vcmp.f32 s4, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #5.5
+ vcmp.f32 s5, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s6, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #7.5
+ vcmp.f32 s7, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #8.0
+ vcmp.f32 s8, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #9.5
+ vcmp.f32 s9, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #10.0
+ vcmp.f32 s10, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #11.5
+ vcmp.f32 s11, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s12, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #13.5
+ vcmp.f32 s13, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #14.0
+ vcmp.f32 s14, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #1.5
+ vcmp.f32 s15, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s16, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s17, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #4.0
+ vcmp.f32 s18, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #5.5
+ vcmp.f32 s19, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s20, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #7.5
+ vcmp.f32 s21, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #8.0
+ vcmp.f32 s22, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #9.5
+ vcmp.f32 s23, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #10.0
+ vcmp.f32 s24, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #11.5
+ vcmp.f32 s25, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s26, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #13.5
+ vcmp.f32 s27, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #14.0
+ vcmp.f32 s28, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #1.5
+ vcmp.f32 s29, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s30, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s31, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg3_error_loop
+
+ /* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest3LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+
+ /* Yield to increase test coverage. */
+ movs r0, #0x01
+ ldr r1, =0xe000ed04 /* NVIC_ICSR. */
+ lsl r0, r0, #28 /* Shift to PendSV bit. */
+ str r0, [r1]
+ dsb
+ pop { r0, r1 }
+
+ /* Start again. */
+ b reg3_loop
+
+ reg3_error_loop:
+ b reg3_error_loop
+ nop
+ ltorg /* Create a literal pool to ensure that the constants accessed in the above
+ * code are not out of range. */
+
+/*-----------------------------------------------------------*/
+
+vRegTest4Asm:
+ /* Fill the core registers with known values. */
+ movs r0, #0
+ movs r1, #1
+ movs r2, #2
+ movs r3, #3
+ movs r4, #4
+ movs r5, #5
+ movs r6, #6
+ movs r7, #7
+ mov r8, #8
+ mov r9, #9
+ movs r10, #10
+ movs r11, #11
+ movs r12, #12
+
+ /* Fill the FPU registers with known values. */
+ vmov.f32 s0, #1.5
+ vmov.f32 s2, #2.0
+ vmov.f32 s3, #3.0
+ vmov.f32 s4, #4.5
+ vmov.f32 s5, #5.0
+ vmov.f32 s6, #6.0
+ vmov.f32 s7, #7.5
+ vmov.f32 s8, #8.0
+ vmov.f32 s9, #9.0
+ vmov.f32 s10, #10.5
+ vmov.f32 s11, #11.0
+ vmov.f32 s12, #12.0
+ vmov.f32 s13, #13.5
+ vmov.f32 s14, #14.0
+ vmov.f32 s15, #1.0
+ vmov.f32 s16, #2.5
+ vmov.f32 s17, #3.0
+ vmov.f32 s18, #4.0
+ vmov.f32 s19, #5.5
+ vmov.f32 s20, #6.0
+ vmov.f32 s21, #7.0
+ vmov.f32 s22, #8.5
+ vmov.f32 s23, #9.0
+ vmov.f32 s24, #10.0
+ vmov.f32 s25, #11.5
+ vmov.f32 s26, #12.0
+ vmov.f32 s27, #13.0
+ vmov.f32 s28, #14.5
+ vmov.f32 s29, #1.0
+ vmov.f32 s30, #2.0
+ vmov.f32 s31, #3.5
+
+ reg4_loop:
+ /* Verify that core registers contain correct values. */
+ cmp r0, #0
+ bne reg4_error_loop
+ cmp r1, #1
+ bne reg4_error_loop
+ cmp r2, #2
+ bne reg4_error_loop
+ cmp r3, #3
+ bne reg4_error_loop
+ cmp r4, #4
+ bne reg4_error_loop
+ cmp r5, #5
+ bne reg4_error_loop
+ cmp r6, #6
+ bne reg4_error_loop
+ cmp r7, #7
+ bne reg4_error_loop
+ cmp r8, #8
+ bne reg4_error_loop
+ cmp r9, #9
+ bne reg4_error_loop
+ cmp r10, #10
+ bne reg4_error_loop
+ cmp r11, #11
+ bne reg4_error_loop
+ cmp r12, #12
+ bne reg4_error_loop
+
+ /* Verify that FPU registers contain correct values. */
+ vmov.f32 s1, #1.5
+ vcmp.f32 s0, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s2, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #3.0
+ vcmp.f32 s3, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #4.5
+ vcmp.f32 s4, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #5.0
+ vcmp.f32 s5, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s6, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #7.5
+ vcmp.f32 s7, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #8.0
+ vcmp.f32 s8, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #9.0
+ vcmp.f32 s9, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #10.5
+ vcmp.f32 s10, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #11.0
+ vcmp.f32 s11, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s12, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #13.5
+ vcmp.f32 s13, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #14.0
+ vcmp.f32 s14, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #1.0
+ vcmp.f32 s15, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #2.5
+ vcmp.f32 s16, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #3.0
+ vcmp.f32 s17, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #4.0
+ vcmp.f32 s18, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #5.5
+ vcmp.f32 s19, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s20, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #7.0
+ vcmp.f32 s21, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #8.5
+ vcmp.f32 s22, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #9.0
+ vcmp.f32 s23, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #10.0
+ vcmp.f32 s24, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #11.5
+ vcmp.f32 s25, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s26, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #13.0
+ vcmp.f32 s27, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #14.5
+ vcmp.f32 s28, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #1.0
+ vcmp.f32 s29, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s30, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s31, s1
+ vmrs APSR_nzcv, FPSCR
+ bne reg4_error_loop
+
+ /* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest4LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0, r1 }
+
+ /* Start again. */
+ b reg4_loop
+
+ reg4_error_loop:
+ b reg4_error_loop
+ nop
+ ltorg /* Create a literal pool to ensure that the constants accessed in the above
+ * code are not out of range. */
+
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/RVDS/reg_tests_asm.s b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/RVDS/reg_tests_asm.s
new file mode 100644
index 0000000000..7bf441fdf3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/RVDS/reg_tests_asm.s
@@ -0,0 +1,956 @@
+;/*
+; * FreeRTOS V202212.00
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; */
+
+;/*
+; * "Reg test" tasks - These fill the registers with known values, then check
+; * that each register maintains its expected value for the lifetime of the
+; * task. Each task uses a different set of values. The reg test tasks execute
+; * with a very low priority, so get preempted very frequently. A register
+; * containing an unexpected value is indicative of an error in the context
+; * switching mechanism.
+; */
+;/*-----------------------------------------------------------*/
+
+ IMPORT ulRegTest1LoopCounter
+ IMPORT ulRegTest2LoopCounter
+ IMPORT ulRegTest3LoopCounter
+ IMPORT ulRegTest4LoopCounter
+
+ EXPORT vRegTest1Asm
+ EXPORT vRegTest2Asm
+ EXPORT vRegTest3Asm
+ EXPORT vRegTest4Asm
+
+ AREA REG_TESTS_ASM, CODE, READONLY
+;/*-----------------------------------------------------------*/
+
+vRegTest1Asm
+
+ PRESERVE8
+
+ ;/* Fill the core registers with known values. */
+ movs r0, #100
+ movs r1, #101
+ movs r2, #102
+ movs r3, #103
+ movs r4, #104
+ movs r5, #105
+ movs r6, #106
+ movs r7, #107
+ mov r8, #108
+ mov r9, #109
+ mov r10, #110
+ mov r11, #111
+ mov r12, #112
+
+ ;/* Fill the FPU registers with known values. */
+ vmov.f32 s1, #1.5
+ vmov.f32 s2, #2.5
+ vmov.f32 s3, #3.5
+ vmov.f32 s4, #4.5
+ vmov.f32 s5, #5.5
+ vmov.f32 s6, #6.5
+ vmov.f32 s7, #7.5
+ vmov.f32 s8, #8.5
+ vmov.f32 s9, #9.5
+ vmov.f32 s10, #10.5
+ vmov.f32 s11, #11.5
+ vmov.f32 s12, #12.5
+ vmov.f32 s13, #13.5
+ vmov.f32 s14, #14.5
+ vmov.f32 s15, #1.0
+ vmov.f32 s16, #2.0
+ vmov.f32 s17, #3.0
+ vmov.f32 s18, #4.0
+ vmov.f32 s19, #5.0
+ vmov.f32 s20, #6.0
+ vmov.f32 s21, #7.0
+ vmov.f32 s22, #8.0
+ vmov.f32 s23, #9.0
+ vmov.f32 s24, #10.0
+ vmov.f32 s25, #11.0
+ vmov.f32 s26, #12.0
+ vmov.f32 s27, #13.0
+ vmov.f32 s28, #14.0
+ vmov.f32 s29, #1.5
+ vmov.f32 s30, #2.5
+ vmov.f32 s31, #3.5
+
+reg1_loop
+ ;/* Verify that core registers contain correct values. */
+ cmp r0, #100
+ bne.w reg1_error_loop
+ cmp r1, #101
+ bne.w reg1_error_loop
+ cmp r2, #102
+ bne.w reg1_error_loop
+ cmp r3, #103
+ bne.w reg1_error_loop
+ cmp r4, #104
+ bne.w reg1_error_loop
+ cmp r5, #105
+ bne.w reg1_error_loop
+ cmp r6, #106
+ bne.w reg1_error_loop
+ cmp r7, #107
+ bne.w reg1_error_loop
+ cmp r8, #108
+ bne.w reg1_error_loop
+ cmp r9, #109
+ bne.w reg1_error_loop
+ cmp r10, #110
+ bne.w reg1_error_loop
+ cmp r11, #111
+ bne.w reg1_error_loop
+ cmp r12, #112
+ bne.w reg1_error_loop
+
+ ;/* Verify that FPU registers contain correct values. */
+ vmov.f32 s0, #1.5 ;/* s0 = 1.5. */
+ vcmp.f32 s1, s0 ;/* Compare s0 and s1. */
+ vmrs APSR_nzcv, FPSCR ;/* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne.w to work. */
+ bne.w reg1_error_loop
+ vmov.f32 s0, #2.5
+ vcmp.f32 s2, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #3.5
+ vcmp.f32 s3, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #4.5
+ vcmp.f32 s4, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #5.5
+ vcmp.f32 s5, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #6.5
+ vcmp.f32 s6, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #7.5
+ vcmp.f32 s7, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #8.5
+ vcmp.f32 s8, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #9.5
+ vcmp.f32 s9, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #10.5
+ vcmp.f32 s10, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #11.5
+ vcmp.f32 s11, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #12.5
+ vcmp.f32 s12, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #13.5
+ vcmp.f32 s13, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #14.5
+ vcmp.f32 s14, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #1.0
+ vcmp.f32 s15, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #2.0
+ vcmp.f32 s16, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #3.0
+ vcmp.f32 s17, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #4.0
+ vcmp.f32 s18, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #5.0
+ vcmp.f32 s19, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #6.0
+ vcmp.f32 s20, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #7.0
+ vcmp.f32 s21, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #8.0
+ vcmp.f32 s22, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #9.0
+ vcmp.f32 s23, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #10.0
+ vcmp.f32 s24, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #11.0
+ vcmp.f32 s25, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #12.0
+ vcmp.f32 s26, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #13.0
+ vcmp.f32 s27, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #14.0
+ vcmp.f32 s28, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #1.5
+ vcmp.f32 s29, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #2.5
+ vcmp.f32 s30, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+ vmov.f32 s0, #3.5
+ vcmp.f32 s31, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg1_error_loop
+
+ ;/* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest1LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+
+ ;/* Yield to increase test coverage. */
+ movs r0, #0x01
+ ldr r1, =0xe000ed04 ;/* NVIC_ICSR. */
+ lsls r0, #28 ;/* Shift to PendSV bit. */
+ str r0, [r1]
+ dsb
+ pop { r0, r1 }
+
+ ;/* Start again. */
+ b reg1_loop
+
+reg1_error_loop
+ b reg1_error_loop
+ LTORG
+;/*-----------------------------------------------------------*/
+
+vRegTest2Asm
+
+ PRESERVE8
+
+ ;/* Fill the core registers with known values. */
+ movs r0, #0
+ movs r1, #1
+ movs r2, #2
+ movs r3, #3
+ movs r4, #4
+ movs r5, #5
+ movs r6, #6
+ movs r7, #7
+ mov r8, #8
+ mov r9, #9
+ movs r10, #10
+ movs r11, #11
+ movs r12, #12
+
+ ;/* Fill the FPU registers with known values. */
+ vmov.f32 s1, #1.0
+ vmov.f32 s2, #2.0
+ vmov.f32 s3, #3.0
+ vmov.f32 s4, #4.0
+ vmov.f32 s5, #5.0
+ vmov.f32 s6, #6.0
+ vmov.f32 s7, #7.0
+ vmov.f32 s8, #8.0
+ vmov.f32 s9, #9.0
+ vmov.f32 s10, #10.0
+ vmov.f32 s11, #11.0
+ vmov.f32 s12, #12.0
+ vmov.f32 s13, #13.0
+ vmov.f32 s14, #14.0
+ vmov.f32 s15, #1.5
+ vmov.f32 s16, #2.5
+ vmov.f32 s17, #3.5
+ vmov.f32 s18, #4.5
+ vmov.f32 s19, #5.5
+ vmov.f32 s20, #6.5
+ vmov.f32 s21, #7.5
+ vmov.f32 s22, #8.5
+ vmov.f32 s23, #9.5
+ vmov.f32 s24, #10.5
+ vmov.f32 s25, #11.5
+ vmov.f32 s26, #12.5
+ vmov.f32 s27, #13.5
+ vmov.f32 s28, #14.5
+ vmov.f32 s29, #1.0
+ vmov.f32 s30, #2.0
+ vmov.f32 s31, #3.0
+
+reg2_loop
+ ;/* Verify that core registers contain correct values. */
+ cmp r0, #0
+ bne.w reg2_error_loop
+ cmp r1, #1
+ bne.w reg2_error_loop
+ cmp r2, #2
+ bne.w reg2_error_loop
+ cmp r3, #3
+ bne.w reg2_error_loop
+ cmp r4, #4
+ bne.w reg2_error_loop
+ cmp r5, #5
+ bne.w reg2_error_loop
+ cmp r6, #6
+ bne.w reg2_error_loop
+ cmp r7, #7
+ bne.w reg2_error_loop
+ cmp r8, #8
+ bne.w reg2_error_loop
+ cmp r9, #9
+ bne.w reg2_error_loop
+ cmp r10, #10
+ bne.w reg2_error_loop
+ cmp r11, #11
+ bne.w reg2_error_loop
+ cmp r12, #12
+ bne.w reg2_error_loop
+
+ ;/* Verify that FPU registers contain correct values. */
+ vmov.f32 s0, #1.0
+ vcmp.f32 s1, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #2.0
+ vcmp.f32 s2, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #3.0
+ vcmp.f32 s3, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #4.0
+ vcmp.f32 s4, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #5.0
+ vcmp.f32 s5, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #6.0
+ vcmp.f32 s6, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #7.0
+ vcmp.f32 s7, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #8.0
+ vcmp.f32 s8, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #9.0
+ vcmp.f32 s9, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #10.0
+ vcmp.f32 s10, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #11.0
+ vcmp.f32 s11, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #12.0
+ vcmp.f32 s12, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #13.0
+ vcmp.f32 s13, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #14.0
+ vcmp.f32 s14, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #1.5
+ vcmp.f32 s15, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #2.5
+ vcmp.f32 s16, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #3.5
+ vcmp.f32 s17, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #4.5
+ vcmp.f32 s18, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #5.5
+ vcmp.f32 s19, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #6.5
+ vcmp.f32 s20, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #7.5
+ vcmp.f32 s21, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #8.5
+ vcmp.f32 s22, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #9.5
+ vcmp.f32 s23, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #10.5
+ vcmp.f32 s24, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #11.5
+ vcmp.f32 s25, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #12.5
+ vcmp.f32 s26, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #13.5
+ vcmp.f32 s27, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #14.5
+ vcmp.f32 s28, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #1.0
+ vcmp.f32 s29, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #2.0
+ vcmp.f32 s30, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+ vmov.f32 s0, #3.0
+ vcmp.f32 s31, s0
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg2_error_loop
+
+ ;/* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest2LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0, r1 }
+
+ ;/* Start again. */
+ b reg2_loop
+
+reg2_error_loop
+ b reg2_error_loop
+ LTORG
+;/*-----------------------------------------------------------*/
+
+vRegTest3Asm
+
+ PRESERVE8
+
+ ;/* Fill the core registers with known values. */
+ movs r0, #100
+ movs r1, #101
+ movs r2, #102
+ movs r3, #103
+ movs r4, #104
+ movs r5, #105
+ movs r6, #106
+ movs r7, #107
+ mov r8, #108
+ mov r9, #109
+ mov r10, #110
+ mov r11, #111
+ mov r12, #112
+
+ ;/* Fill the FPU registers with known values. */
+ vmov.f32 s0, #1.5
+ vmov.f32 s2, #2.0
+ vmov.f32 s3, #3.5
+ vmov.f32 s4, #4.0
+ vmov.f32 s5, #5.5
+ vmov.f32 s6, #6.0
+ vmov.f32 s7, #7.5
+ vmov.f32 s8, #8.0
+ vmov.f32 s9, #9.5
+ vmov.f32 s10, #10.0
+ vmov.f32 s11, #11.5
+ vmov.f32 s12, #12.0
+ vmov.f32 s13, #13.5
+ vmov.f32 s14, #14.0
+ vmov.f32 s15, #1.5
+ vmov.f32 s16, #2.0
+ vmov.f32 s17, #3.5
+ vmov.f32 s18, #4.0
+ vmov.f32 s19, #5.5
+ vmov.f32 s20, #6.0
+ vmov.f32 s21, #7.5
+ vmov.f32 s22, #8.0
+ vmov.f32 s23, #9.5
+ vmov.f32 s24, #10.0
+ vmov.f32 s25, #11.5
+ vmov.f32 s26, #12.0
+ vmov.f32 s27, #13.5
+ vmov.f32 s28, #14.0
+ vmov.f32 s29, #1.5
+ vmov.f32 s30, #2.0
+ vmov.f32 s31, #3.5
+
+reg3_loop
+ ;/* Verify that core registers contain correct values. */
+ cmp r0, #100
+ bne.w reg3_error_loop
+ cmp r1, #101
+ bne.w reg3_error_loop
+ cmp r2, #102
+ bne.w reg3_error_loop
+ cmp r3, #103
+ bne.w reg3_error_loop
+ cmp r4, #104
+ bne.w reg3_error_loop
+ cmp r5, #105
+ bne.w reg3_error_loop
+ cmp r6, #106
+ bne.w reg3_error_loop
+ cmp r7, #107
+ bne.w reg3_error_loop
+ cmp r8, #108
+ bne.w reg3_error_loop
+ cmp r9, #109
+ bne.w reg3_error_loop
+ cmp r10, #110
+ bne.w reg3_error_loop
+ cmp r11, #111
+ bne.w reg3_error_loop
+ cmp r12, #112
+ bne.w reg3_error_loop
+
+ ;/* Verify that FPU registers contain correct values. */
+ vmov.f32 s1, #1.5
+ vcmp.f32 s0, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s2, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s3, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #4.0
+ vcmp.f32 s4, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #5.5
+ vcmp.f32 s5, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s6, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #7.5
+ vcmp.f32 s7, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #8.0
+ vcmp.f32 s8, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #9.5
+ vcmp.f32 s9, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #10.0
+ vcmp.f32 s10, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #11.5
+ vcmp.f32 s11, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s12, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #13.5
+ vcmp.f32 s13, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #14.0
+ vcmp.f32 s14, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #1.5
+ vcmp.f32 s15, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s16, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s17, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #4.0
+ vcmp.f32 s18, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #5.5
+ vcmp.f32 s19, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s20, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #7.5
+ vcmp.f32 s21, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #8.0
+ vcmp.f32 s22, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #9.5
+ vcmp.f32 s23, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #10.0
+ vcmp.f32 s24, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #11.5
+ vcmp.f32 s25, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s26, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #13.5
+ vcmp.f32 s27, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #14.0
+ vcmp.f32 s28, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #1.5
+ vcmp.f32 s29, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s30, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s31, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg3_error_loop
+
+ ;/* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest3LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+
+ ;/* Yield to increase test coverage. */
+ movs r0, #0x01
+ ldr r1, =0xe000ed04 ;/* NVIC_ICSR. */
+ lsls r0, #28 ;/* Shift to PendSV bit. */
+ str r0, [r1]
+ dsb
+ pop { r0, r1 }
+
+ ;/* Start again. */
+ b reg3_loop
+
+reg3_error_loop
+ b reg3_error_loop
+ LTORG
+;/*-----------------------------------------------------------*/
+
+vRegTest4Asm
+
+ PRESERVE8
+
+ ;/* Fill the core registers with known values. */
+ movs r0, #0
+ movs r1, #1
+ movs r2, #2
+ movs r3, #3
+ movs r4, #4
+ movs r5, #5
+ movs r6, #6
+ movs r7, #7
+ mov r8, #8
+ mov r9, #9
+ movs r10, #10
+ movs r11, #11
+ movs r12, #12
+
+ ;/* Fill the FPU registers with known values. */
+ vmov.f32 s0, #1.5
+ vmov.f32 s2, #2.0
+ vmov.f32 s3, #3.0
+ vmov.f32 s4, #4.5
+ vmov.f32 s5, #5.0
+ vmov.f32 s6, #6.0
+ vmov.f32 s7, #7.5
+ vmov.f32 s8, #8.0
+ vmov.f32 s9, #9.0
+ vmov.f32 s10, #10.5
+ vmov.f32 s11, #11.0
+ vmov.f32 s12, #12.0
+ vmov.f32 s13, #13.5
+ vmov.f32 s14, #14.0
+ vmov.f32 s15, #1.0
+ vmov.f32 s16, #2.5
+ vmov.f32 s17, #3.0
+ vmov.f32 s18, #4.0
+ vmov.f32 s19, #5.5
+ vmov.f32 s20, #6.0
+ vmov.f32 s21, #7.0
+ vmov.f32 s22, #8.5
+ vmov.f32 s23, #9.0
+ vmov.f32 s24, #10.0
+ vmov.f32 s25, #11.5
+ vmov.f32 s26, #12.0
+ vmov.f32 s27, #13.0
+ vmov.f32 s28, #14.5
+ vmov.f32 s29, #1.0
+ vmov.f32 s30, #2.0
+ vmov.f32 s31, #3.5
+
+reg4_loop
+ ;/* Verify that core registers contain correct values. */
+ cmp r0, #0
+ bne.w reg4_error_loop
+ cmp r1, #1
+ bne.w reg4_error_loop
+ cmp r2, #2
+ bne.w reg4_error_loop
+ cmp r3, #3
+ bne.w reg4_error_loop
+ cmp r4, #4
+ bne.w reg4_error_loop
+ cmp r5, #5
+ bne.w reg4_error_loop
+ cmp r6, #6
+ bne.w reg4_error_loop
+ cmp r7, #7
+ bne.w reg4_error_loop
+ cmp r8, #8
+ bne.w reg4_error_loop
+ cmp r9, #9
+ bne.w reg4_error_loop
+ cmp r10, #10
+ bne.w reg4_error_loop
+ cmp r11, #11
+ bne.w reg4_error_loop
+ cmp r12, #12
+ bne.w reg4_error_loop
+
+ ;/* Verify that FPU registers contain correct values. */
+ vmov.f32 s1, #1.5
+ vcmp.f32 s0, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s2, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #3.0
+ vcmp.f32 s3, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #4.5
+ vcmp.f32 s4, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #5.0
+ vcmp.f32 s5, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s6, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #7.5
+ vcmp.f32 s7, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #8.0
+ vcmp.f32 s8, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #9.0
+ vcmp.f32 s9, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #10.5
+ vcmp.f32 s10, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #11.0
+ vcmp.f32 s11, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s12, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #13.5
+ vcmp.f32 s13, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #14.0
+ vcmp.f32 s14, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #1.0
+ vcmp.f32 s15, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #2.5
+ vcmp.f32 s16, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #3.0
+ vcmp.f32 s17, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #4.0
+ vcmp.f32 s18, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #5.5
+ vcmp.f32 s19, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #6.0
+ vcmp.f32 s20, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #7.0
+ vcmp.f32 s21, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #8.5
+ vcmp.f32 s22, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #9.0
+ vcmp.f32 s23, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #10.0
+ vcmp.f32 s24, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #11.5
+ vcmp.f32 s25, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #12.0
+ vcmp.f32 s26, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #13.0
+ vcmp.f32 s27, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #14.5
+ vcmp.f32 s28, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #1.0
+ vcmp.f32 s29, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #2.0
+ vcmp.f32 s30, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+ vmov.f32 s1, #3.5
+ vcmp.f32 s31, s1
+ vmrs APSR_nzcv, FPSCR
+ bne.w reg4_error_loop
+
+ ;/* Everything passed, inc the loop counter. */
+ push { r0, r1 }
+ ldr r0, =ulRegTest4LoopCounter
+ ldr r1, [r0]
+ adds r1, r1, #1
+ str r1, [r0]
+ pop { r0, r1 }
+
+ ;/* Start again. */
+ b reg4_loop
+
+reg4_error_loop
+ b reg4_error_loop
+ LTORG
+;/*-----------------------------------------------------------*/
+
+ END
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c
index 2677c86f06..761b1ba237 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/app_main.c
@@ -32,12 +32,16 @@
/* Demo includes. */
#include "mpu_demo.h"
+#include "reg_tests.h"
void app_main( void )
{
/* Start the MPU demo. */
vStartMPUDemo();
+ /* Start register tests. */
+ vStartRegTests();
+
/* Start the scheduler. */
vTaskStartScheduler();
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c
new file mode 100644
index 0000000000..d4efebfb67
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.c
@@ -0,0 +1,376 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Reg test includes. */
+#include "reg_tests.h"
+
+/* Hardware includes. */
+#include "main.h"
+
+/*
+ * Functions that implement reg test tasks.
+ */
+static void prvRegTest1Task( void * pvParameters );
+static void prvRegTest2Task( void * pvParameters );
+static void prvRegTest3Task( void * pvParameters );
+static void prvRegTest4Task( void * pvParameters );
+
+/*
+ * Check task periodically checks that reg tests tasks
+ * are running fine.
+ */
+static void prvCheckTask( void * pvParameters );
+
+/*
+ * Functions implemented in assembly.
+ */
+extern void vRegTest1Asm( void );
+extern void vRegTest2Asm( void );
+extern void vRegTest3Asm( void );
+extern void vRegTest4Asm( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Priority of the check task.
+ */
+#define CHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+
+/*
+ * Frequency of check task.
+ */
+#define NO_ERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 5000UL ) )
+#define ERROR_CHECK_TASK_PERIOD ( pdMS_TO_TICKS( 200UL ) )
+
+/*
+ * Parameters passed to reg test tasks.
+ */
+#define REG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
+#define REG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
+#define REG_TEST_TASK_3_PARAMETER ( ( void * ) 0x12348765 )
+#define REG_TEST_TASK_4_PARAMETER ( ( void * ) 0x43215678 )
+/*-----------------------------------------------------------*/
+
+/*
+ * The following variables are used to communicate the status of the register
+ * test tasks to the check task. If the variables keep incrementing, then the
+ * register test tasks have not discovered any errors. If a variable stops
+ * incrementing, then an error has been found.
+ */
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+volatile unsigned long ulRegTest3LoopCounter = 0UL, ulRegTest4LoopCounter = 0UL;
+
+/**
+ * Counter to keep a count of how may times the check task loop has detected
+ * error.
+ */
+volatile unsigned long ulCheckTaskLoops = 0UL;
+/*-----------------------------------------------------------*/
+
+void vStartRegTests( void )
+{
+static StackType_t xRegTest1TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+static StackType_t xRegTest2TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+static StackType_t xRegTest3TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+static StackType_t xRegTest4TaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+static StackType_t xCheckTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+
+TaskParameters_t xRegTest1TaskParameters =
+{
+ .pvTaskCode = prvRegTest1Task,
+ .pcName = "RegTest1",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = REG_TEST_TASK_1_PARAMETER,
+ .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+ .puxStackBuffer = xRegTest1TaskStack,
+ .xRegions = {
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
+ }
+};
+TaskParameters_t xRegTest2TaskParameters =
+{
+ .pvTaskCode = prvRegTest2Task,
+ .pcName = "RegTest2",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = REG_TEST_TASK_2_PARAMETER,
+ .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+ .puxStackBuffer = xRegTest2TaskStack,
+ .xRegions = {
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
+ }
+};
+TaskParameters_t xRegTest3TaskParameters =
+{
+ .pvTaskCode = prvRegTest3Task,
+ .pcName = "RegTest3",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = REG_TEST_TASK_3_PARAMETER,
+ .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+ .puxStackBuffer = xRegTest3TaskStack,
+ .xRegions = {
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
+ }
+};
+TaskParameters_t xRegTest4TaskParameters =
+{
+ .pvTaskCode = prvRegTest4Task,
+ .pcName = "RegTest4",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = REG_TEST_TASK_4_PARAMETER,
+ .uxPriority = tskIDLE_PRIORITY | portPRIVILEGE_BIT,
+ .puxStackBuffer = xRegTest4TaskStack,
+ .xRegions = {
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
+ }
+};
+
+TaskParameters_t xCheckTaskParameters =
+{
+ .pvTaskCode = prvCheckTask,
+ .pcName = "Check",
+ .usStackDepth = configMINIMAL_STACK_SIZE,
+ .pvParameters = NULL,
+ .uxPriority = ( CHECK_TASK_PRIORITY | portPRIVILEGE_BIT ),
+ .puxStackBuffer = xCheckTaskStack,
+ .xRegions = {
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
+ }
+};
+
+ xTaskCreateRestricted( &( xRegTest1TaskParameters ), NULL );
+ xTaskCreateRestricted( &( xRegTest2TaskParameters ), NULL );
+ xTaskCreateRestricted( &( xRegTest3TaskParameters ), NULL );
+ xTaskCreateRestricted( &( xRegTest4TaskParameters ), NULL );
+ xTaskCreateRestricted( &( xCheckTaskParameters ), NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest1Task( void * pvParameters )
+{
+ /* Although the reg tests are written in assembly, its entry
+ * point is written in C for convenience of checking that the
+ * task parameter is being passed in correctly. */
+ if( pvParameters == REG_TEST_TASK_1_PARAMETER )
+ {
+ /* Start the part of the test that is written in assembler. */
+ vRegTest1Asm();
+ }
+
+ /* The following line will only execute if the task parameter
+ * is found to be incorrect. The check task will detect that
+ * the reg test loop counter is not being incremented and flag
+ * an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest2Task( void * pvParameters )
+{
+ /* Although the reg tests are written in assembly, its entry
+ * point is written in C for convenience of checking that the
+ * task parameter is being passed in correctly. */
+ if( pvParameters == REG_TEST_TASK_2_PARAMETER )
+ {
+ /* Start the part of the test that is written in assembler. */
+ vRegTest2Asm();
+ }
+
+ /* The following line will only execute if the task parameter
+ * is found to be incorrect. The check task will detect that
+ * the reg test loop counter is not being incremented and flag
+ * an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest3Task( void * pvParameters )
+{
+ /* Although the reg tests are written in assembly, its entry
+ * point is written in C for convenience of checking that the
+ * task parameter is being passed in correctly. */
+ if( pvParameters == REG_TEST_TASK_3_PARAMETER )
+ {
+ /* Start the part of the test that is written in assembler. */
+ vRegTest3Asm();
+ }
+
+ /* The following line will only execute if the task parameter
+ * is found to be incorrect. The check task will detect that
+ * the reg test loop counter is not being incremented and flag
+ * an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTest4Task( void * pvParameters )
+{
+ /* Although the reg tests are written in assembly, its entry
+ * point is written in C for convenience of checking that the
+ * task parameter is being passed in correctly. */
+ if( pvParameters == REG_TEST_TASK_4_PARAMETER )
+ {
+ /* Start the part of the test that is written in assembler. */
+ vRegTest4Asm();
+ }
+
+ /* The following line will only execute if the task parameter
+ * is found to be incorrect. The check task will detect that
+ * the reg test loop counter is not being incremented and flag
+ * an error. */
+ vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void * pvParameters )
+{
+TickType_t xDelayPeriod = NO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+unsigned long ulErrorFound = pdFALSE;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+static unsigned long ulLastRegTest3Value = 0, ulLastRegTest4Value = 0;
+
+ /* Just to stop compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Initialize xLastExecutionTime so the first call to vTaskDelayUntil()
+ * works correctly. */
+ xLastExecutionTime = xTaskGetTickCount();
+
+ /* Cycle for ever, delaying then checking all the other tasks are still
+ * operating without error. The onboard LED is toggled on each iteration.
+ * If an error is detected then the delay period is decreased from
+ * mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has
+ * the effect of increasing the rate at which the onboard LED toggles, and
+ * in so doing gives visual feedback of the system status. */
+ for( ;; )
+ {
+ /* Delay until it is time to execute again. */
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+ /* Check that the register test 1 task is still running. */
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+ {
+ ulErrorFound |= 1UL << 0UL;
+ }
+ ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+ /* Check that the register test 2 task is still running. */
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+ {
+ ulErrorFound |= 1UL << 1UL;
+ }
+ ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+ /* Check that the register test 3 task is still running. */
+ if( ulLastRegTest3Value == ulRegTest3LoopCounter )
+ {
+ ulErrorFound |= 1UL << 2UL;
+ }
+ ulLastRegTest3Value = ulRegTest3LoopCounter;
+
+ /* Check that the register test 4 task is still running. */
+ if( ulLastRegTest4Value == ulRegTest4LoopCounter )
+ {
+ ulErrorFound |= 1UL << 3UL;
+ }
+ ulLastRegTest4Value = ulRegTest4LoopCounter;
+
+
+ /* Toggle the green LED to give an indication of the system status.
+ * If the LED toggles every NO_ERROR_CHECK_TASK_PERIOD milliseconds
+ * then everything is ok. A faster toggle indicates an error. */
+ HAL_GPIO_TogglePin( LD1_GPIO_Port, LD1_Pin );
+
+ if( ulErrorFound != pdFALSE )
+ {
+ /* An error has been detected in one of the tasks - flash the LED
+ * at a higher frequency to give visible feedback that something has
+ * gone wrong (it might just be that the loop back connector required
+ * by the comtest tasks has not been fitted). */
+ xDelayPeriod = ERROR_CHECK_TASK_PERIOD;
+
+ /* Turn on Red LED to indicate error. */
+ HAL_GPIO_WritePin( LD3_GPIO_Port, LD3_Pin, GPIO_PIN_SET );
+
+ /* Increment error detection count. */
+ ulCheckTaskLoops++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h
new file mode 100644
index 0000000000..0837aad72d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Demo/reg_tests.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef REG_TESTS_H
+#define REG_TESTS_H
+
+/**
+ * @brief Creates all the tasks for reg tests.
+ */
+void vStartRegTests( void );
+
+#endif /* REG_TESTS_H */
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject
index 852a26954b..55f883f974 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.cproject
@@ -10,6 +10,7 @@
+
@@ -18,9 +19,9 @@
-
-
-
+
+
+
@@ -76,6 +77,32 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -122,6 +149,7 @@
+
@@ -152,4 +180,4 @@
-
+
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project
index 21d9ba2d4b..23501c2b08 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/GCC/.project
@@ -53,6 +53,15 @@
+
+ 1680067487361
+ Demo
+ 9
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-GCC
+
+
1594591511105
FreeRTOS
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd
index 926cc66f86..e380c1f250 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewd
@@ -1,1419 +1,1546 @@
- 3
-
- FreeRTOSDemo
-
- ARM
-
- 1
-
- C-SPY
- 2
-
- 29
- 1
- 1
-
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- 2
-
- 1
- 1
- 1
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- CADI_ID
- 2
-
- 0
- 1
- 1
-
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- CMSISDAP_ID
- 2
-
- 4
- 1
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- GDBSERVER_ID
- 2
-
- 0
- 1
- 1
-
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- IJET_ID
- 2
-
- 8
- 1
- 1
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- 2
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- 1
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- LMIFTDI_ID
- 2
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- 2
- 1
- 1
-
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- PEMICRO_ID
- 2
-
- 3
- 1
- 1
-
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- STLINK_ID
- 2
-
- 4
- 1
- 1
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diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp
index 22a161f088..e7f646ee74 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/IAR/FreeRTOSDemo.ewp
@@ -11,9 +11,13 @@
General
3
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+ 34
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Config
@@ -1074,6 +1073,12 @@
Demo
+
+ IAR
+
+ $PROJ_DIR$\..\..\Demo\IAR\reg_tests_asm.s
+
+
$PROJ_DIR$\..\..\Demo\app_main.c
@@ -1086,6 +1091,12 @@
$PROJ_DIR$\..\..\Demo\mpu_demo.h
+
+ $PROJ_DIR$\..\..\Demo\reg_tests.c
+
+
+ $PROJ_DIR$\..\..\Demo\reg_tests.h
+
FreeRTOS
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx
index c6e38d3ca2..fce0ba11e9 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvoptx
@@ -10,7 +10,7 @@
*.s*; *.src; *.a*
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diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx
index d3c763b3da..ab02655a84 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil/FreeRTOSDemo.uvprojx
@@ -10,14 +10,14 @@
FreeRTOSDemo
0x4
ARM-ADS
- 6130001::V6.13.1::.\ARMCLANG
+ 6180000::V6.18::ARMCLANG
1
STM32H743ZITx
STMicroelectronics
- Keil.STM32H7xx_DFP.2.4.0
- https://www.keil.com/pack/
+ Keil.STM32H7xx_DFP.3.0.0
+ http://www.keil.com/pack/
IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE
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diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.sct b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.sct
new file mode 100644
index 0000000000..333a44cc2c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.sct
@@ -0,0 +1,45 @@
+; Flash Layout
+;
+; ---------------------
+; | Privileged Code |
+; ---------------------
+; | Unprivileged Code |
+; ---------------------
+;
+; RAM Layout
+;
+; ---------------------
+; | Privileged Data |
+; ---------------------
+; | Unprivileged Data |
+; ---------------------
+
+LR_APP 0x08000000 0x00200000 ; load region size_region
+{
+ ER_IROM_PRIVILEGED 0x08000000
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ *(privileged_functions)
+ }
+
+ ER_IROM_FREERTOS_SYSTEM_CALLS 0x08008000 FIXED
+ {
+ *(freertos_system_calls)
+ }
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+ ER_IROM_UNPRIVILEGED +0
+ {
+ .ANY (+RO)
+ }
+
+ RW_IRAM_PRIVILEGED 0x20000000
+ {
+ *(privileged_data)
+ }
+
+ RW_IRAM_UNPRIVILEGED 0x20008000
+ {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvoptx
new file mode 100644
index 0000000000..5d0b06c3ed
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvoptx
@@ -0,0 +1,1928 @@
+
+
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+ ### uVision Project, (C) Keil Software
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diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvprojx
new file mode 100644
index 0000000000..ba0ab789ce
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/FreeRTOSDemo.uvprojx
@@ -0,0 +1,1129 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ FreeRTOSDemo
+ 0x4
+ ARM-ADS
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+ STM32H743ZITx
+ STMicroelectronics
+ Keil.STM32H7xx_DFP.3.0.0
+ http://www.keil.com/pack/
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+
+
+
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+
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+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma2d.c
+
+
+ stm32h7xx_ll_exti.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c
+
+
+ stm32h7xx_ll_fmc.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_fmc.c
+
+
+ stm32h7xx_ll_gpio.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c
+
+
+ stm32h7xx_ll_hrtim.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_hrtim.c
+
+
+ stm32h7xx_ll_i2c.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_i2c.c
+
+
+ stm32h7xx_ll_lptim.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_lptim.c
+
+
+ stm32h7xx_ll_lpuart.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_lpuart.c
+
+
+ stm32h7xx_ll_mdma.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_mdma.c
+
+
+ stm32h7xx_ll_opamp.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_opamp.c
+
+
+ stm32h7xx_ll_pwr.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_pwr.c
+
+
+ stm32h7xx_ll_rcc.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c
+
+
+ stm32h7xx_ll_rng.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rng.c
+
+
+ stm32h7xx_ll_rtc.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rtc.c
+
+
+ stm32h7xx_ll_sdmmc.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_sdmmc.c
+
+
+ stm32h7xx_ll_spi.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_spi.c
+
+
+ stm32h7xx_ll_swpmi.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_swpmi.c
+
+
+ stm32h7xx_ll_tim.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_tim.c
+
+
+ stm32h7xx_ll_usart.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c
+
+
+ stm32h7xx_ll_usb.c
+ 1
+ ..\..\ST_Code\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c
+
+
+
+
+ Startup
+
+
+ memfault_handler.c
+ 1
+ .\memfault_handler.c
+
+
+ startup_stm32h743xx.s
+ 2
+ .\startup_stm32h743xx.s
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c
new file mode 100644
index 0000000000..6c14c6ff08
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/memfault_handler.c
@@ -0,0 +1,66 @@
+/*
+ * FreeRTOS V202212.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include
+
+extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base;
+extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit;
+
+/* Memory map needed for MPU setup. Must must match the one defined in
+ * the scatter-loading file (FreeRTOSDemo.sct). */
+const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x08000000;
+const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x08200000;
+const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000;
+const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20020000;
+
+const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x08000000;
+const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x08008000;
+const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000;
+const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20008000;
+
+const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base );
+const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Mem fault handler.
+ */
+void MemManage_Handler( void );
+/*-----------------------------------------------------------*/
+
+__asm void MemManage_Handler( void )
+{
+ extern vHandleMemoryFault;
+
+ PRESERVE8
+
+ tst lr, #4
+ ite eq
+ mrseq r0, msp
+ mrsne r0, psp
+ b vHandleMemoryFault
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/startup_stm32h743xx.s b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/startup_stm32h743xx.s
new file mode 100644
index 0000000000..266479eef3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/Projects/Keil_V5/startup_stm32h743xx.s
@@ -0,0 +1,611 @@
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name : startup_stm32h743xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/lexicon.txt b/lexicon.txt
index f3574d5432..fe87f51d0e 100644
--- a/lexicon.txt
+++ b/lexicon.txt
@@ -64,6 +64,7 @@ ascii
asf
asm
asn
+aspr
ast
async
atmega
@@ -818,6 +819,7 @@ fpga
fpidiv
fprintf
fpu
+fpscr
fr
framming
france
@@ -1235,6 +1237,7 @@ lsb
lserialputstring
lsize
lsl
+lsls
lsr
lstringlength
ltd
@@ -3130,6 +3133,7 @@ vbuttonisrhandler
vcellularconnecttask
vcellulardemotask
vclearemactxbuffer
+vcmp
vconfiguretimerforruntimestats
vcore
vcreatesuicidaltask
@@ -3183,6 +3187,7 @@ vmaindeleteme
vmainpoststopprocessing
vmemchecktask
vmov
+vmrs
vodafone
votademotask
vpartestinitialise